Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications

Hdl Handle:
http://hdl.handle.net/10149/58344
Title:
Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications
Authors:
Xu, D. (Donglai); Bentley, J. P. (John); Gao, R. L. (Rui)
Affiliation:
University of Teesside
Citation:
Xu, D., Bentley J. P. and Gao, R. (2003) 'Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications', IEEE Transactions on Consumer Electronics, 49 (4), pp.1383-1390.
Publisher:
Institute of Electrical and Electronics Engineers
Journal:
IEEE Transactions on Consumer Electronics
Issue Date:
Nov-2003
URI:
http://hdl.handle.net/10149/58344
DOI:
10.1109/TCE.2003.1261244
Abstract:
A reconfigurable hardware implementation of a high-parallel architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low power dissipation and low cost, thus primarily aiming at video-based mobile applications. The architecture employs a dual-register/buffer technique to reduce preload and alignment cycles and a high-parallel pipeline to reduce power consumption of redundant memory access. As an example, a content-based full-search blockmatching algorithm has been mapped onto this architecture using a 16-PE array. This has the ability to calculate the motion vectors of 20fps QCIF video sequences in real time at 8.2 MHz clock rate with 36.76mw power dissipation using a Xilinx Spartan II FPGA.
Type:
Article
Keywords:
MPEG-4; motion estimation; VLSI; full search
ISSN:
0098-3063
Rights:
Author can archive publisher's version/PDF. For full details see http://www.sherpa.ac.uk/romeo/ [Accessed 04/01/2010]
Citation Count:
6 [Scopus, 04/01/2010]

Full metadata record

DC FieldValue Language
dc.contributor.authorXu, D. (Donglai)-
dc.contributor.authorBentley, J. P. (John)-
dc.contributor.authorGao, R. L. (Rui)-
dc.date.accessioned2009-04-01T10:49:37Z-
dc.date.available2009-04-01T10:49:37Z-
dc.date.issued2003-11-
dc.identifier.citationIEEE Transactions on Consumer Electronics; 49 (4): 1383-1390-
dc.identifier.issn0098-3063-
dc.identifier.doi10.1109/TCE.2003.1261244-
dc.identifier.urihttp://hdl.handle.net/10149/58344-
dc.description.abstractA reconfigurable hardware implementation of a high-parallel architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low power dissipation and low cost, thus primarily aiming at video-based mobile applications. The architecture employs a dual-register/buffer technique to reduce preload and alignment cycles and a high-parallel pipeline to reduce power consumption of redundant memory access. As an example, a content-based full-search blockmatching algorithm has been mapped onto this architecture using a 16-PE array. This has the ability to calculate the motion vectors of 20fps QCIF video sequences in real time at 8.2 MHz clock rate with 36.76mw power dissipation using a Xilinx Spartan II FPGA.-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.rightsAuthor can archive publisher's version/PDF. For full details see http://www.sherpa.ac.uk/romeo/ [Accessed 04/01/2010]-
dc.subjectMPEG-4-
dc.subjectmotion estimation-
dc.subjectVLSI-
dc.subjectfull search-
dc.titleReconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications-
dc.typeArticle-
dc.contributor.departmentUniversity of Teesside-
dc.identifier.journalIEEE Transactions on Consumer Electronics-
ref.assessmentRAE 2008-
ref.citationcount6 [Scopus, 04/01/2010]-
or.citation.harvardXu, D., Bentley J. P. and Gao, R. (2003) 'Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications', IEEE Transactions on Consumer Electronics, 49 (4), pp.1383-1390.-
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