A VLSI-based parallel architecture for block-matching motion estimation in video coding applications

Hdl Handle:
http://hdl.handle.net/10149/99333
Title:
A VLSI-based parallel architecture for block-matching motion estimation in video coding applications
Book Title:
Progress in computer research
Authors:
Xu, D. (Donglai); Noras, J. M. (James); Booth, W. (William)
Editors:
Columbus, F. (Frank)
Affiliation:
University of Bradford. Department of Electronic and Electrical Engineering.
Citation:
Xu, D., Noras, J. M. and Booth, W. (2001) 'A VLSI-based parallel architecture for block-matching motion estimation in video coding applications', in Columbus, F. (ed) Progress in computer research. New York: Nova Science Publishers, pp.9-16.
Publisher:
Nova Science Publishers
Issue Date:
2001
URI:
http://hdl.handle.net/10149/99333
Additional Links:
https://www.novapublishers.com/catalog/product_info.php?products_id=710
Abstract:
In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
Type:
Meetings and Proceedings; Book Chapter
Language:
en
Keywords:
VLSI; parallel processing architecture; three-step search algorithm; motion estimation algorithm
Series/Report no.:
2
ISBN:
1590330110
Citation Count:
0 [Web of Science, 19/05/2010]

Full metadata record

DC FieldValue Language
dc.contributor.authorXu, D. (Donglai)en
dc.contributor.authorNoras, J. M. (James)en
dc.contributor.authorBooth, W. (William)en
dc.contributor.editorColumbus, F. (Frank)en
dc.date.accessioned2010-05-19T14:58:05Z-
dc.date.available2010-05-19T14:58:05Z-
dc.date.issued2001-
dc.identifier.isbn1590330110-
dc.identifier.urihttp://hdl.handle.net/10149/99333-
dc.description.abstractIn this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.en
dc.language.isoenen
dc.publisherNova Science Publishersen
dc.relation.ispartofseries2-
dc.relation.urlhttps://www.novapublishers.com/catalog/product_info.php?products_id=710en
dc.subjectVLSIen
dc.subjectparallel processing architectureen
dc.subjectthree-step search algorithmen
dc.subjectmotion estimation algorithmen
dc.titleA VLSI-based parallel architecture for block-matching motion estimation in video coding applicationsen
dc.typeMeetings and Proceedingsen
dc.typeBook Chapteren
dc.contributor.departmentUniversity of Bradford. Department of Electronic and Electrical Engineering.en
dc.title.bookProgress in computer researchen
ref.citationcount0 [Web of Science, 19/05/2010]en
or.citation.harvardXu, D., Noras, J. M. and Booth, W. (2001) 'A VLSI-based parallel architecture for block-matching motion estimation in video coding applications', in Columbus, F. (ed) Progress in computer research. New York: Nova Science Publishers, pp.9-16.-
prism.startingPage9-
prism.endingPage16-
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