VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

Hdl Handle:
http://hdl.handle.net/10149/99809
Title:
VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding
Book Title:
ICECS 2001: 8th IEEE international conference on electronics, circuits and systems, vols I-III, Conference proceedings
Authors:
Xu, D. (Donglai); Bentley, J. P. (John)
Affiliation:
Teesside University. School of Science and Technology.
Citation:
Xu, D. and Bentley, J. P. (2001) 'VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding', The 8th IEEE international conference on electronics, circuits and systems, Malta, September 2 - 5, 2001 in 8th IEEE international conference on electronics, circuits and systems, vols I-III, Conference proceedings. IEEE, pp.217-220.
Publisher:
IEEE
Conference:
The 8th IEEE international conference on electronics, circuits and systems, St. Julians, Malta, September 2 - 5, 2001
Issue Date:
Sep-2001
URI:
http://hdl.handle.net/10149/99809
DOI:
10.1109/ICECS.2001.957719
Abstract:
In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
Type:
Meetings and Proceedings; Book Chapter
Language:
en
Keywords:
VLSI; motion estimation algorithm; low bit-rate; video coding
ISBN:
0780370570
Rights:
Author can archive publisher's version/PDF. For full details see http://www.sherpa.ac.uk/romeo/ [Accessed 25/05/2010]
Citation Count:
0 [Web of Science, 25/05/2010]

Full metadata record

DC FieldValue Language
dc.contributor.authorXu, D. (Donglai)en
dc.contributor.authorBentley, J. P. (John)en
dc.date.accessioned2010-05-25T14:58:06Z-
dc.date.available2010-05-25T14:58:06Z-
dc.date.issued2001-09-
dc.identifier.isbn0780370570-
dc.identifier.doi10.1109/ICECS.2001.957719-
dc.identifier.urihttp://hdl.handle.net/10149/99809-
dc.description.abstractIn this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.en
dc.language.isoenen
dc.publisherIEEEen
dc.rightsAuthor can archive publisher's version/PDF. For full details see http://www.sherpa.ac.uk/romeo/ [Accessed 25/05/2010]en
dc.subjectVLSIen
dc.subjectmotion estimation algorithmen
dc.subjectlow bit-rateen
dc.subjectvideo codingen
dc.titleVLSI-based parallel architecture for block-matching motion estimation in low bit-rate video codingen
dc.typeMeetings and Proceedingsen
dc.typeBook Chapteren
dc.contributor.departmentTeesside University. School of Science and Technology.en
dc.title.bookICECS 2001: 8th IEEE international conference on electronics, circuits and systems, vols I-III, Conference proceedingsen
dc.identifier.conferenceThe 8th IEEE international conference on electronics, circuits and systems, St. Julians, Malta, September 2 - 5, 2001en
ref.citationcount0 [Web of Science, 25/05/2010]en
or.citation.harvardXu, D. and Bentley, J. P. (2001) 'VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding', The 8th IEEE international conference on electronics, circuits and systems, Malta, September 2 - 5, 2001 in 8th IEEE international conference on electronics, circuits and systems, vols I-III, Conference proceedings. IEEE, pp.217-220.-
prism.startingPage217-
prism.endingPage220-
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